dp8390.h

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00001 /*
00002  * Copyright (c) 2009 Lukas Mejdrech
00003  * Copyright (c) 2011 Martin Decky
00004  * All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  *
00010  * - Redistributions of source code must retain the above copyright
00011  *   notice, this list of conditions and the following disclaimer.
00012  * - Redistributions in binary form must reproduce the above copyright
00013  *   notice, this list of conditions and the following disclaimer in the
00014  *   documentation and/or other materials provided with the distribution.
00015  * - The name of the author may not be used to endorse or promote products
00016  *   derived from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
00019  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
00020  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
00021  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
00023  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
00024  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
00025  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00026  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
00027  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00028  */
00029 
00030 /*
00031  * This code is based upon the NE2000 driver for MINIX,
00032  * distributed according to a BSD-style license.
00033  *
00034  * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
00035  * Copyright (c) 1992, 1994 Philip Homburg
00036  * Copyright (c) 1996 G. Falzoni
00037  *
00038  */
00039 
00048 #ifndef __NET_NETIF_DP8390_H__
00049 #define __NET_NETIF_DP8390_H__
00050 
00051 #include <fibril_synch.h>
00052 #include <adt/list.h>
00053 #include <net/packet.h>
00054 #include <netif_skel.h>
00055 
00057 #define NAME  "ne2000"
00058 
00060 #define NE2K_IO_SIZE  0x0020
00061 
00063 #define ETH_ADDR  6
00064 
00065 /* National Semiconductor DP8390 Network Interface Controller. */
00066 
00068 #define DP_CR     0x00  
00069 #define DP_CLDA0  0x01  
00070 #define DP_CLDA1  0x02  
00071 #define DP_BNRY   0x03  
00072 #define DP_TSR    0x04  
00073 #define DP_NCR    0x05  
00074 #define DP_FIFO   0x06  
00075 #define DP_ISR    0x07  
00076 #define DP_CRDA0  0x08  
00077 #define DP_CRDA1  0x09  
00078 #define DP_RSR    0x0c  
00079 #define DP_CNTR0  0x0d  
00080 #define DP_CNTR1  0x0e  
00081 #define DP_CNTR2  0x0f  
00084 #define DP_PSTART  0x01  
00085 #define DP_PSTOP   0x02  
00086 #define DP_TPSR    0x04  
00087 #define DP_TBCR0   0x05  
00088 #define DP_TBCR1   0x06  
00089 #define DP_RSAR0   0x08  
00090 #define DP_RSAR1   0x09  
00091 #define DP_RBCR0   0x0a  
00092 #define DP_RBCR1   0x0b  
00093 #define DP_RCR     0x0c  
00094 #define DP_TCR     0x0d  
00095 #define DP_DCR     0x0e  
00096 #define DP_IMR     0x0f  
00099 #define DP_PAR0  0x01  
00100 #define DP_PAR1  0x02  
00101 #define DP_PAR2  0x03  
00102 #define DP_PAR3  0x04  
00103 #define DP_PAR4  0x05  
00104 #define DP_PAR5  0x06  
00105 #define DP_CURR  0x07  
00106 #define DP_MAR0  0x08  
00107 #define DP_MAR1  0x09  
00108 #define DP_MAR2  0x0a  
00109 #define DP_MAR3  0x0b  
00110 #define DP_MAR4  0x0c  
00111 #define DP_MAR5  0x0d  
00112 #define DP_MAR6  0x0e  
00113 #define DP_MAR7  0x0f  
00115 /* Bits in Command Register */
00116 #define CR_STP       0x01  
00117 #define CR_STA       0x02  
00118 #define CR_TXP       0x04  
00119 #define CR_DMA       0x38  
00120 #define CR_DM_NOP    0x00  
00121 #define CR_DM_RR     0x08  
00122 #define CR_DM_RW     0x10  
00123 #define CR_DM_SP     0x18  
00124 #define CR_DM_ABORT  0x20  
00125 #define CR_PS        0xc0  
00126 #define CR_PS_P0     0x00  
00127 #define CR_PS_P1     0x40  
00128 #define CR_PS_P2     0x80  
00129 #define CR_PS_T1     0xc0  
00131 /* Bits in Interrupt State Register */
00132 #define ISR_PRX  0x01  
00133 #define ISR_PTX  0x02  
00134 #define ISR_RXE  0x04  
00135 #define ISR_TXE  0x08  
00136 #define ISR_OVW  0x10  
00137 #define ISR_CNT  0x20  
00138 #define ISR_RDC  0x40  
00139 #define ISR_RST  0x80  
00141 /* Bits in Interrupt Mask Register */
00142 #define IMR_PRXE  0x01  
00143 #define IMR_PTXE  0x02  
00144 #define IMR_RXEE  0x04  
00145 #define IMR_TXEE  0x08  
00146 #define IMR_OVWE  0x10  
00147 #define IMR_CNTE  0x20  
00148 #define IMR_RDCE  0x40  
00150 /* Bits in Data Configuration Register */
00151 #define DCR_WTS        0x01  
00152 #define DCR_BYTEWIDE   0x00  
00153 #define DCR_WORDWIDE   0x01  
00154 #define DCR_BOS        0x02  
00155 #define DCR_LTLENDIAN  0x00  
00156 #define DCR_BIGENDIAN  0x02  
00157 #define DCR_LAS        0x04  
00158 #define DCR_BMS        0x08  
00159 #define DCR_AR         0x10  
00160 #define DCR_FTS        0x60  
00161 #define DCR_2BYTES     0x00  
00162 #define DCR_4BYTES     0x40  
00163 #define DCR_8BYTES     0x20  
00164 #define DCR_12BYTES    0x60  
00166 /* Bits in Transmit Configuration Register */
00167 #define TCR_CRC        0x01  
00168 #define TCR_ELC        0x06  
00169 #define TCR_NORMAL     0x00  
00170 #define TCR_INTERNAL   0x02  
00171 #define TCR_0EXTERNAL  0x04  
00172 #define TCR_1EXTERNAL  0x06  
00173 #define TCR_ATD        0x08  
00174 #define TCR_OFST       0x10  
00176 /* Bits in Interrupt Status Register */
00177 #define TSR_PTX  0x01  
00178 #define TSR_DFR  0x02  
00179 #define TSR_COL  0x04  
00180 #define TSR_ABT  0x08  
00181 #define TSR_CRS  0x10  
00182 #define TSR_FU   0x20  
00183 #define TSR_CDH  0x40  
00184 #define TSR_OWC  0x80  
00186 /* Bits in Receive Configuration Register */
00187 #define RCR_SEP  0x01  
00188 #define RCR_AR   0x02  
00189 #define RCR_AB   0x04  
00190 #define RCR_AM   0x08  
00191 #define RCR_PRO  0x10  
00192 #define RCR_MON  0x20  
00194 /* Bits in Receive Status Register */
00195 #define RSR_PRX  0x01  
00196 #define RSR_CRC  0x02  
00197 #define RSR_FAE  0x04  
00198 #define RSR_FO   0x08  
00199 #define RSR_MPA  0x10  
00200 #define RSR_PHY  0x20  
00201 #define RSR_DIS  0x40  
00202 #define RSR_DFR  0x80  
00204 typedef struct {
00205         /* Device configuration */
00206         void *port;
00207         void *data_port;
00208         int irq;
00209         uint8_t mac[ETH_ADDR];
00210         
00211         uint8_t start_page;  
00212         uint8_t stop_page;   
00214         /* Send queue */
00215         struct {
00216                 bool dirty;    
00217                 size_t size;   
00218                 uint8_t page;  
00219         } sq;
00220         fibril_mutex_t sq_mutex;
00221         fibril_condvar_t sq_cv;
00222         
00223         /* Driver run-time variables */
00224         bool probed;
00225         bool up;
00226         
00227         /* Device statistics */
00228         device_stats_t stats;
00229         uint64_t misses;     
00230         uint64_t underruns;  
00231         uint64_t overruns;   
00232 } ne2k_t;
00233 
00234 typedef struct {
00235         link_t link;
00236         packet_t *packet;
00237 } frame_t;
00238 
00239 extern int ne2k_probe(ne2k_t *, void *, int);
00240 extern int ne2k_up(ne2k_t *);
00241 extern void ne2k_down(ne2k_t *);
00242 extern void ne2k_send(ne2k_t *, packet_t *);
00243 extern link_t *ne2k_interrupt(ne2k_t *, uint8_t, uint8_t);
00244 
00245 #endif
00246 

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