ohci_regs.h

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00001 /*
00002  * Copyright (c) 2011 Jan Vesely
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * - Redistributions of source code must retain the above copyright
00010  *   notice, this list of conditions and the following disclaimer.
00011  * - Redistributions in binary form must reproduce the above copyright
00012  *   notice, this list of conditions and the following disclaimer in the
00013  *   documentation and/or other materials provided with the distribution.
00014  * - The name of the author may not be used to endorse or promote products
00015  *   derived from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
00019  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
00020  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
00022  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
00023  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
00024  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00025  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
00026  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  */
00034 #ifndef DRV_OHCI_OHCI_REGS_H
00035 #define DRV_OHCI_OHCI_REGS_H
00036 #include <stdint.h>
00037 
00039 typedef struct ohci_regs {
00040         const volatile uint32_t revision;
00041         volatile uint32_t control;
00042 #define C_CSBR_MASK (0x3) /* Control-bulk service ratio */
00043 #define C_CSBR_1_1  (0x0)
00044 #define C_CSBR_1_2  (0x1)
00045 #define C_CSBR_1_3  (0x2)
00046 #define C_CSBR_1_4  (0x3)
00047 #define C_CSBR_SHIFT (0)
00048 
00049 #define C_PLE (1 << 2)   /* Periodic list enable */
00050 #define C_IE  (1 << 3)   /* Isochronous enable */
00051 #define C_CLE (1 << 4)   /* Control list enable */
00052 #define C_BLE (1 << 5)   /* Bulk list enable */
00053 
00054 #define C_HCFS_MASK        (0x3) /* Host controller functional state */
00055 #define C_HCFS_RESET       (0x0)
00056 #define C_HCFS_RESUME      (0x1)
00057 #define C_HCFS_OPERATIONAL (0x2)
00058 #define C_HCFS_SUSPEND     (0x3)
00059 #define C_HCFS_SHIFT       (6)
00060 
00061 #define C_IR  (1 << 8)   /* Interrupt routing, make sure it's 0 */
00062 #define C_RWC (1 << 9)   /* Remote wakeup connected, host specific */
00063 #define C_RWE (1 << 10)  /* Remote wakeup enable */
00064 
00065         volatile uint32_t command_status;
00066 #define CS_HCR (1 << 0)   /* Host controller reset */
00067 #define CS_CLF (1 << 1)   /* Control list filled */
00068 #define CS_BLF (1 << 2)   /* Bulk list filled */
00069 #define CS_OCR (1 << 3)   /* Ownership change request */
00070 #define CS_SOC_MASK (0x3) /* Scheduling overrun count */
00071 #define CS_SOC_SHIFT (16)
00072 
00077         volatile uint32_t interrupt_status;
00078         volatile uint32_t interrupt_enable;
00079         volatile uint32_t interrupt_disable;
00080 #define I_SO   (1 << 0)   /* Scheduling overrun */
00081 #define I_WDH  (1 << 1)   /* Done head write-back */
00082 #define I_SF   (1 << 2)   /* Start of frame */
00083 #define I_RD   (1 << 3)   /* Resume detect */
00084 #define I_UE   (1 << 4)   /* Unrecoverable error */
00085 #define I_FNO  (1 << 5)   /* Frame number overflow */
00086 #define I_RHSC (1 << 6)   /* Root hub status change */
00087 #define I_OC   (1 << 30)  /* Ownership change */
00088 #define I_MI   (1 << 31)  /* Master interrupt (all/any interrupts) */
00089 
00091         volatile uint32_t hcca;
00092 #define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
00093 
00095         const volatile uint32_t periodic_current;
00096 
00098         volatile uint32_t control_head;
00099 
00101         volatile uint32_t control_current;
00102 
00104         volatile uint32_t bulk_head;
00105 
00107         volatile uint32_t bulk_current;
00108 
00110         const volatile uint32_t done_head;
00111 
00113         volatile uint32_t fm_interval;
00114 #define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
00115 #define FMI_FI_SHIFT (0)
00116 #define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */
00117 #define FMI_FSMPS_SHIFT (16)
00118 #define FMI_TOGGLE_FLAG (1 << 31)
00119 
00121         const volatile uint32_t fm_remaining;
00122 #define FMR_FR_MASK FMI_FI_MASK
00123 #define FMR_FR_SHIFT FMI_FI_SHIFT
00124 #define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG
00125 
00127         const volatile uint32_t fm_number;
00128 #define FMN_NUMBER_MASK (0xffff)
00129 
00131         volatile uint32_t periodic_start;
00132 #define PS_PS_MASK (0x3fff) /* bit time when periodic get priority (0x3e67) */
00133 
00135         volatile uint32_t ls_threshold;
00136 #define LST_LST_MASK (0x7fff)
00137 
00139         volatile uint32_t rh_desc_a;
00140 #define RHDA_NDS_MASK (0xff) /* Number of downstream ports, max 15 */
00141 #define RHDA_NDS_SHIFT (0)
00142 #define RHDA_PSM_FLAG  (1 << 8)  /* Power switching mode: 0-global, 1-per port*/
00143 #define RHDA_NPS_FLAG  (1 << 9)  /* No power switch: 1-power on, 0-use PSM*/
00144 #define RHDA_DT_FLAG   (1 << 10) /* 1-Compound device, must be 0 */
00145 #define RHDA_OCPM_FLAG (1 << 11) /* Over-current mode: 0-global, 1-per port */
00146 #define RHDA_NOCP      (1 << 12) /* OC control: 0-use OCPM, 1-OC off */
00147 #define RHDA_POTPGT_MASK (0xff)  /* Power on to power good time */
00148 #define RHDA_POTPGT_SHIFT (24)
00149 
00151         volatile uint32_t rh_desc_b;
00152 #define RHDB_DR_MASK (0xffff) /* Device removable mask */
00153 #define RHDB_DR_SHIFT (0)
00154 #define RHDB_PCC_MASK (0xffff) /* Power control mask */
00155 #define RHDB_PCC_SHIFT (16)
00156 
00157 /* Port device removable status */
00158 #define RHDB_DR_FLAG(port) (((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
00159 /* Port power control status: 1-per port power control, 0-global power switch */
00160 #define RHDB_PPC_FLAG(port) (((1 << port) & RHDB_DR_MASK) << RHDB_DR_SHIFT)
00161 
00163         volatile uint32_t rh_status;
00164 #define RHS_LPS_FLAG  (1 <<  0)/* read: 0,
00165                                 * write: 0-no effect,
00166                                 *        1-turn off port power for ports
00167                                 *        specified in PPCM(RHDB), or all ports,
00168                                 *        if power is set globally */
00169 #define RHS_CLEAR_PORT_POWER RHS_LPS_FLAG /* synonym for the above */
00170 #define RHS_OCI_FLAG  (1 <<  1)/* Over-current indicator, if per-port: 0 */
00171 #define RHS_DRWE_FLAG (1 << 15)/* read: 0-connect status change does not wake HC
00172                                 *       1-connect status change wakes HC
00173                                 * write: 1-set DRWE, 0-no effect */
00174 #define RHS_SET_DRWE RHS_DRWE_FLAG
00175 #define RHS_LPSC_FLAG (1 << 16)/* read: 0,
00176                                 * write: 0-no effect
00177                                 *        1-turn on port power for ports
00178                                 *        specified in PPCM(RHDB), or all ports,
00179                                 *        if power is set globally */
00180 #define RHS_SET_PORT_POWER RHS_LPSC_FLAG /* synonym for the above */
00181 #define RHS_OCIC_FLAG (1 << 17)/* Over-current indicator change   */
00182 #define RHS_CLEAR_DRWE (1 << 31)
00183 
00185         volatile uint32_t rh_port_status[];
00186 #define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
00187                                 * w: 1-clear port enable, 0-nothing */
00188 #define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG
00189 #define RHPS_PES_FLAG (1 << 1) /* r: port enable status
00190                                 * w: 1-set port enable, 0-nothing */
00191 #define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG
00192 #define RHPS_PSS_FLAG (1 << 2) /* r: port suspend status
00193                                 * w: 1-set port suspend, 0-nothing */
00194 #define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG
00195 #define RHPS_POCI_FLAG (1 << 3) /* r: port over-current (if reports are per-port
00196                                  * w: 1-clear port suspend (start resume
00197                                  *      if suspened)
00198                                  *    0-nothing */
00199 #define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG
00200 #define RHPS_PRS_FLAG (1 << 4) /* r: port reset status
00201                                 * w: 1-set port reset, 0-nothing */
00202 #define RHPS_SET_PORT_RESET RHPS_PRS_FLAG
00203 #define RHPS_PPS_FLAG (1 << 8) /* r: port power status
00204                                 * w: 1-set port power, 0-nothing */
00205 #define RHPS_SET_PORT_POWER RHPS_PPS_FLAG
00206 #define RHPS_LSDA_FLAG (1 << 9) /* r: low speed device attached
00207                                  * w: 1-clear port power, 0-nothing */
00208 #define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG
00209 #define RHPS_CSC_FLAG  (1 << 16) /* connect status change Write-Clean */
00210 #define RHPS_PESC_FLAG (1 << 17) /* port enable status change WC */
00211 #define RHPS_PSSC_FLAG (1 << 18) /* port suspend status change WC */
00212 #define RHPS_OCIC_FLAG (1 << 19) /* port over-current change WC */
00213 #define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */
00214 #define RHPS_CHANGE_WC_MASK 0x1f0000
00215 } __attribute__((packed)) ohci_regs_t;
00216 #endif
00217 

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