dp8390.h

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/*
 * Copyright (c) 2009 Lukas Mejdrech
 * Copyright (c) 2011 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * This code is based upon the NE2000 driver for MINIX,
 * distributed according to a BSD-style license.
 *
 * Copyright (c) 1987, 1997, 2006 Vrije Universiteit
 * Copyright (c) 1992, 1994 Philip Homburg
 * Copyright (c) 1996 G. Falzoni
 *
 */

#ifndef __NET_NETIF_DP8390_H__
#define __NET_NETIF_DP8390_H__

#include <fibril_synch.h>
#include <adt/list.h>
#include <net/packet.h>
#include <netif_skel.h>

#define NAME  "ne2000"

#define NE2K_IO_SIZE  0x0020

#define ETH_ADDR  6

/* National Semiconductor DP8390 Network Interface Controller. */

#define DP_CR     0x00  
#define DP_CLDA0  0x01  
#define DP_CLDA1  0x02  
#define DP_BNRY   0x03  
#define DP_TSR    0x04  
#define DP_NCR    0x05  
#define DP_FIFO   0x06  
#define DP_ISR    0x07  
#define DP_CRDA0  0x08  
#define DP_CRDA1  0x09  
#define DP_RSR    0x0c  
#define DP_CNTR0  0x0d  
#define DP_CNTR1  0x0e  
#define DP_CNTR2  0x0f  
#define DP_PSTART  0x01  
#define DP_PSTOP   0x02  
#define DP_TPSR    0x04  
#define DP_TBCR0   0x05  
#define DP_TBCR1   0x06  
#define DP_RSAR0   0x08  
#define DP_RSAR1   0x09  
#define DP_RBCR0   0x0a  
#define DP_RBCR1   0x0b  
#define DP_RCR     0x0c  
#define DP_TCR     0x0d  
#define DP_DCR     0x0e  
#define DP_IMR     0x0f  
#define DP_PAR0  0x01  
#define DP_PAR1  0x02  
#define DP_PAR2  0x03  
#define DP_PAR3  0x04  
#define DP_PAR4  0x05  
#define DP_PAR5  0x06  
#define DP_CURR  0x07  
#define DP_MAR0  0x08  
#define DP_MAR1  0x09  
#define DP_MAR2  0x0a  
#define DP_MAR3  0x0b  
#define DP_MAR4  0x0c  
#define DP_MAR5  0x0d  
#define DP_MAR6  0x0e  
#define DP_MAR7  0x0f  
/* Bits in Command Register */
#define CR_STP       0x01  
#define CR_STA       0x02  
#define CR_TXP       0x04  
#define CR_DMA       0x38  
#define CR_DM_NOP    0x00  
#define CR_DM_RR     0x08  
#define CR_DM_RW     0x10  
#define CR_DM_SP     0x18  
#define CR_DM_ABORT  0x20  
#define CR_PS        0xc0  
#define CR_PS_P0     0x00  
#define CR_PS_P1     0x40  
#define CR_PS_P2     0x80  
#define CR_PS_T1     0xc0  
/* Bits in Interrupt State Register */
#define ISR_PRX  0x01  
#define ISR_PTX  0x02  
#define ISR_RXE  0x04  
#define ISR_TXE  0x08  
#define ISR_OVW  0x10  
#define ISR_CNT  0x20  
#define ISR_RDC  0x40  
#define ISR_RST  0x80  
/* Bits in Interrupt Mask Register */
#define IMR_PRXE  0x01  
#define IMR_PTXE  0x02  
#define IMR_RXEE  0x04  
#define IMR_TXEE  0x08  
#define IMR_OVWE  0x10  
#define IMR_CNTE  0x20  
#define IMR_RDCE  0x40  
/* Bits in Data Configuration Register */
#define DCR_WTS        0x01  
#define DCR_BYTEWIDE   0x00  
#define DCR_WORDWIDE   0x01  
#define DCR_BOS        0x02  
#define DCR_LTLENDIAN  0x00  
#define DCR_BIGENDIAN  0x02  
#define DCR_LAS        0x04  
#define DCR_BMS        0x08  
#define DCR_AR         0x10  
#define DCR_FTS        0x60  
#define DCR_2BYTES     0x00  
#define DCR_4BYTES     0x40  
#define DCR_8BYTES     0x20  
#define DCR_12BYTES    0x60  
/* Bits in Transmit Configuration Register */
#define TCR_CRC        0x01  
#define TCR_ELC        0x06  
#define TCR_NORMAL     0x00  
#define TCR_INTERNAL   0x02  
#define TCR_0EXTERNAL  0x04  
#define TCR_1EXTERNAL  0x06  
#define TCR_ATD        0x08  
#define TCR_OFST       0x10  
/* Bits in Interrupt Status Register */
#define TSR_PTX  0x01  
#define TSR_DFR  0x02  
#define TSR_COL  0x04  
#define TSR_ABT  0x08  
#define TSR_CRS  0x10  
#define TSR_FU   0x20  
#define TSR_CDH  0x40  
#define TSR_OWC  0x80  
/* Bits in Receive Configuration Register */
#define RCR_SEP  0x01  
#define RCR_AR   0x02  
#define RCR_AB   0x04  
#define RCR_AM   0x08  
#define RCR_PRO  0x10  
#define RCR_MON  0x20  
/* Bits in Receive Status Register */
#define RSR_PRX  0x01  
#define RSR_CRC  0x02  
#define RSR_FAE  0x04  
#define RSR_FO   0x08  
#define RSR_MPA  0x10  
#define RSR_PHY  0x20  
#define RSR_DIS  0x40  
#define RSR_DFR  0x80  
typedef struct {
        /* Device configuration */
        void *port;
        void *data_port;
        int irq;
        uint8_t mac[ETH_ADDR];
        
        uint8_t start_page;  
        uint8_t stop_page;   
        /* Send queue */
        struct {
                bool dirty;    
                size_t size;   
                uint8_t page;  
        } sq;
        fibril_mutex_t sq_mutex;
        fibril_condvar_t sq_cv;
        
        /* Driver run-time variables */
        bool probed;
        bool up;
        
        /* Device statistics */
        device_stats_t stats;
        uint64_t misses;     
        uint64_t underruns;  
        uint64_t overruns;   
} ne2k_t;

typedef struct {
        link_t link;
        packet_t *packet;
} frame_t;

extern int ne2k_probe(ne2k_t *, void *, int);
extern int ne2k_up(ne2k_t *);
extern void ne2k_down(ne2k_t *);
extern void ne2k_send(ne2k_t *, packet_t *);
extern link_t *ne2k_interrupt(ne2k_t *, uint8_t, uint8_t);

#endif

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